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FUJITSU SEMICONDUCTOR DATA SHEET
DS04-21350-1E
ASSP
Dual Serial Input
PLL FrequencySynthesizer MB15F03L
s DESCRIPITON
The Fujitsu MB15F03L is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 1800MHz and a 250MHz prescalers. A 64/65 or a 128/129 for the 1800MHz prescaler, and a 16/17 or a 32/33 for 250MHz prescaler can be selected that enables pulse swallow operation. The latest BiCMOS process technology is used, resuItantly a supply current is limited as low as 5.0mA typ. at a supply voltage of 3.0V. Furthermore, a super charger circuit is included to provide a fast tuning as well as low noise performance. As a result of this, MB15F03L is ideally suitable for digital mobile communications, such as PHS(Personal Handy Phone System), PCN (Personal Communication Network) and PCS(Personal Communication Service).
s FEATURES
* * * * * * * High frequency operation RF synthesizer: 1800MHz max. / IF synthesizer: 250MHz max. Low power supply voltage: VCC = 2.7 to 3.6V Very Low power supply current : ICC = 5.0 mA typ. (Vcc = 3V) Power saving function : Supply current at power saving mode Typ.0.1A (Vcc=3V), Max.10A (IPS1=IPS2) Dual modulus prescaler : 1800MHz prescaler(64/65,128/129) , 250MHz prescaler(16/17,32/33) Serial input 14-bit programmable reference divider: R = 5 to 16,383 Serial input 18-bit programmable divider consisting of: - Binary 7-bit swallow counter: 0 to 127 - Binary 11-bit programmable counter: 5 to 2,047 * On-chip high performance charge pump circuit and phase comparator, achieving high-speed lock-up and low phase noise * On-chip phase control for phase comparator * Wide operating temperature: Ta = -40 to 85C
s PACKAGE
16-pin, Plastic SSOP 16-pin, Plastic BCC
(FPT-16P-M05)
(LCC-16P-M03)
MB15F03L
s PIN ASSIGNMENT
SSOP-16-PIN
GNDRF OSCin GNDIF finIF VccIF LD/fout PSIF DoIF
1 2 3 4
16 15 14
Clock Data LE finRF VccRF XfinRF PSRF DoRF
TOP 13 VIEW 5 12 6 7 8 11 10 9
(FPT-16P-M05)
BCC-16-PIN
GNDRF Clock OSCin GNDIF finIF VCCIF LD/fout PSIF 1 2 3 16 15 14 13 12 Data LE finRF VCCRF XinRF PSRF
TOP VIEW
4 5 6 7 8 11 10 9
DOIF DORF
(LCC-16P-M03)
2
MB15F03L
s PIN DESCRIPTION
Pin No. SSOP-16 1 2 3 4 5 BCC-16 16 1 2 3 4 Pin name GNDRF OSCin GNDIF finIF VccIF I/O - I - I - Ground for RF-PLL section. The programmable reference divider input. TCXO should be connected with a AC coupling capacitor. Ground for the IF-PLL section. Prescaler input pin for the IF-PLL. The connection with VCO should be AC coupling. Power supply voltage input pin for the IF-PLL section. Lock detect signal output (LD) / phase comparator monitoring output (fout) The output signal is selected by a LDS bit in a serial data. LDS bit = "H" ; outputs fout signal LDS bit = "L" ; outputs LD signal Power saving mode control for the IF-PLL section. This pin must be set at "L" Power-ON. (Open is prohibited.) PSIF = "H" ; Normal mode PSIF = "L" ; Power saving mode Charge pump output for the IF-PLL section. Phase characteristics of the phase detector can be reversed by FC-bit. Charge pump output for the RF-PLL section. Phase characteristics of the phase detector can be reversed by FC-bit. Power saving mode control for the RF-PLL section. This pin must be set at "L" Power-ON. (Open is prohibited.) PSRF = "H" ; Normal mode PSRF = "L" ; Power saving mode Prescaler complimentary input for the RF-PLL section. This pin should be grounded via a capacitor. Power supply voltage input pin for the RF-PLL section, the shift register and the oscillator input buffer. When power is OFF, latched data of RFPLL is cancelled. Prescaler input pin for the RF-PLL. The connection with VCO should be AC coupling. Load enable signal input (with the schmitt trigger circuit.) When LE is "H", data in the shift register is transferred to the corresponding latch according to the control bit in a serial data. Serial data input (with the schmitt trigger circuit.) A data is transferred to the corresponding latch (IF-ref counter, IF-prog. counter, RF-ref. counter, RF-prog. counter) according to the control bit in a serial data. Clock input for the 23-bit shift register (with the schmitt trigger circuit.) One bit data is shifted into the shift register on a rising edge of the clock. Descriptions
6
5
LD/fout
O
7
6
PSIF
I
8 9
7 8
DoIF DoRF
O O
10
9
PSRF
I
11 12 13
10 11 12
XfinRF VccRF finRF
I - I
14
13
LE
I
15
14
Data
I
16
15
Clock
I
3
MB15F03L
s BLOCK DIAGRAM
VccIF
5
GNDIF
3
7
PSIF
Intermittent mode control
(IF-PLL)
3-bit latch LDS SWIF FCIF
7-bit latch
11-bit latch
fpIF
Binary 11-bit Binary 7-bit swallow counter programmable counter(IF-PLL) (IF-PLL)
Phase comp.
(IF-PLL)
Charge Super pump charger (IF-PLL)
8 DoIF
Prescaler
finIF 4
(IF-PLL)
16/17,32/33 2-bit latch T1 T2 14-bit latch
frIF Binary 14-bit programmable ref. counter(IF-PLL)
Lock Det.
(IF-PLL)
LDI
2
OSCin
AND OR
frRF
T1
T2
Binary 14-bit programmable ref. counter(RF-PLL)
LDRF
Selector LD frIF frRF fpIF fp RF
6 LD/fout
2-bit latch
finRF 13 XfinRF
11
14-bit latch
Lock Det.
(RF-PLL)
Prescaler 64/65, 128/129 Intermittent mode control
(RF-PLL) (RF-PLL)
LDS SWRF FCRF 3-bit latch
Binary 7-bit swallow counter
(RF-PLL)
Binary 11-bit programmable counter(RF-PLL)
fpRF
Phase comp.
(RF-PLL)
PSRF 10
Charge Super pump (RF-PLL) charger
9 DoRF
7-bit latch
11-bit latch
LE 14
Schmitt circuit
Latch selector
Data 15 Clock 16
Schmitt circuit Schmitt circuit
C N 1
C N 2
23-bit shift register
12 1
VCCRF
GNDRF
Note: SSOP-16 pin
4
MB15F03L
s ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage Input voltage Output voltage Output current Storage temperature Symbol VCC VI VO IO Ido TSTG Rating -0.5 to +4.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -10 to +10 -25 to +25 -55 to +125 Unit V V V mA mA C Except Do Do output Remark
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter Power supply voltage Input voltage Operating temperature Symbol VCC Vi Ta Value Min 2.7 GND -40 Typ 3.0 - - Max 3.6 VCC +85 Unit V V C Note VCCIF=VCCRF
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always yse semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with repect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand.
Handling Precautions
* This device should be transported and stored in anti-static containers. * This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are properly grounded. Cover workerbenches with grounded conductive mats. * Always turn the power supply off before inserting or removing the device from its socket. * Protect leads with a conductive sheet when handling or transporting PC boards with devices.
5
MB15F03L
s ELECTRICAL CHARACTERISTICS
(Vcc=2.7V to 3.6V, Ta=-40C to 85C) Value Unit Typ. Max. 1.5 3.5 0.1*3 0.1*3 -- -- -- -- -- -- -- -- -- -- -- mA -- -- -- 50 100 -- IF-PLL, 50 termination RF-PLL, 50 termination -- Schmitt trigger input Schmitt trigger input -- -- -- -- -- -- IOH=-1.0mA IOL= 1.0mA IDOH =-1.0mA VCC=3.0V, IDOL=1.0mA VCC=3.0V, VOFF=GND to VCC 3 -10 -10 0.5 VCCx0.7+ 0.4 -- VCCx0.7 -- -1.0 -1.0 0 -100 VCC-0.4 -- VCC-0.4 -- -- -- -- -- -- -- -- -- -- -- 10 A 10 250 1800 40 +2 +2 VCC -- VCCx0.3 -0.4 -- VCCx0.3 +1.0 +1.0 +100 0 -- 0.4 -- 0.4 3.0 A V dBm dBm Vp-p MHz
Parameter
Symbol ICCIF*1
Condition finIF = 233.15MHz, fosc = 12MHz finRF = 1800MHz, fosc = 12MHz VccIF current at PSIF ="L" VccRF current at PSIF/RF ="L" IF-PLL RF-PLL
Min. --
Power supply current ICCRF
*2
IpsIF Power saving current
IpsRF
finIF*4 Operating frequency finRF
*4
finIF finRF fOSC VfinIF VfinRF VOSC VIH VIL VIH VIL IIH*5 IIL*5 IIH IIL
*5
OSCin finIF Input sensitivity finRF OSCin Data, Clock, LE PSIF, PSRF Data, Clock, LE, PSIF, PSRF OSCin LD/fout Output voltage DoIF, DoRF High impedance cutoff current DoIF, DoRF
Input voltage
V
Input current
A V V nA
VOH
VOL
VDOH VDOL IOFF
(Continued)
6
MB15F03L
(Continued)
Parameter LD/fout Output current DoIF, DoRF Symbol IOH*5 IOL IDOH*5 IDOL Condition Vcc = 3.0V Vcc = 3.0V Vcc = 3.0V, VDOH = 2.0V , Ta=25C (Vcc=2.7V to 3.6V, Ta=-40C to 85C) Value Unit Typ. Max. -- -- -- -- -- 1.0 -6 mA 8 15 mA
Min. -1.0 -- -11
*1: *2: *3: *4: *5:
Vcc = 3.0V, VDOL = 1.0V, Ta=25C Conditions ; VccIF = 3V, Ta = 25C, in locking state. Conditions ; VccRF = 3V, Ta = 25C, in locking state. fosc = 12.8 MHz , Vcc = 3.0V, Ta = 25C AC coupling with a 1000pF capacitor connected. The symbol "-"(minus) means direction of current flow.
7
MB15F03L
s FUNCTIONAL DESCRIPTIONS
The divide ratio can be calculated using the following equation: fVCO = {(P x N) + A} x fOSC / R fVCO: P: N: A: fOSC: R: (A < N)
Output frequency of external voltage controlled oscillator (VCO) Preset divide ratio of dual modulus prescaler (16 or 32 for IF-PLL, 64 or 128 for RF-PLL) Preset divide ratio of binary 11-bit programmable counter (5 to 2,047) Preset divide ratio of binary 7-bit swallow counter (0 A 127) Reference oscillation frequency Preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383)
Serial Data Input
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF-PLL sections, programmable reference dividers of IF/RF PLL sections are controlled individually. Serial data of binary data is entered through Data pin. On rising edge of clock, one bit of serial data is transferred into the shift register. When load enable signal is high, the data stored in the shift register is transferred to one of latch of them depending upon the control bit data setting. Table1. Control Bit Control bit CN1 L H L H CN2 L L H H Destination of serial data The programmable reference counter for the IF-PLL. The programmable reference counter for the RF-PLL. The programmable counter and the swallow counter for the IF-PLL The programmable counter and the swallow counter for the RF-PLL
Shift Register Configuration
Programmable Reference Counter
LSB Data Flow 1 C N 1 2 C N 2 3 T 1 4 T 2 5 R 1 6 R 2 7 R 3 8 R 4 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 R 5 R 6 R 7 R 8 RRRRRR 9 10 11 12 13 14 X X X X X MSB
CN1, 2 R1 to R14 T1, 2 X
: Control bit : Divide ratio setting bits for the programmable reference counter (5 to 16,383) : Test purpose bit : Dummy bits(Set "0" or "1")
[Table. 1] [Table. 2] [Table.3]
Note: Data input with MSB first.
8
MB15F03L
Programmable Counter
LSB 1 C N 1 2 C N 2 3 L D S 4 5 6 7 A 2 8 A 3 Data Flow 9 A 4 10 A 5 11 A 6 12 A 7 13 N 1 14 N 2 15 N 3 16 N 4 17 N 5 18 N 6 19 N 7 20 N 8 21 N 9 22 N 10 MSB 23 N 11
A S F 1 W C IF / RF IF / RF
CN1, 2 N1 to N11 A1 to A7 SWIF/RF FCIF/RF LDS
: Control bit : Divide ratio setting bits for the programmable counter (5 to 2,047) : Divide ratio setting bits for the swallow counter (0 to 127) : Divide ratio setting bit for the prescaler (16/17 or 32/33 for the IF-PLL, 64/65 or 128/129 for the RF-PLL) : Phase control bit for the phase detector : LD/fout signal select bit
[Table. 1] [Table. 4] [Table. 5] [Table. 6] [Table. 7] [Table. 8]
Note: Data input with MSB first.
Table2. Binary 14-bit Programmable Reference Counter Data Setting Divide ratio (R) 5 6 * 16383 R 14 0 0 * 1 R 13 0 0 * 1 R 12 0 0 * 1 R 11 0 0 * 1 R 10 0 0 * 1 R 9 0 0 * 1 R 8 0 0 * 1 R 7 0 0 * 1 R 6 0 0 * 1 R 5 0 0 * 1 R 4 0 0 * 1 R 3 1 1 * 1 R 2 0 1 * 1 R 1 1 0 * 1
Note: * Divide ratio less than 5 is prohibited. Table.3 Test Purpose Bit Setting T 1 L H L H T 2 L L H H LD/fout pin state Outputs frIF. Outputs frRF. Outputs fpIF. Outputs fpRF.
9
MB15F03L
Table.4 Binary 11-bit Programmable Counter Data Setting Divide ratio (N) 5 6 * 2047 N 11 0 0 * 1 N 10 0 0 * 1 N 9 0 0 * 1 N 8 0 0 * 1 N 7 0 0 * 1 N 6 0 0 * 1 N 5 0 0 * 1 N 4 0 0 * 1 N 3 1 1 * 1 N 2 0 1 * 1 N 1 1 0 * 1
Note: * Divide ratio less than 5 is prohibited. Table.5 Binary 7-bit Swallow Counter Data Setting Divide ratio (A) 0 1 * 127 A 7 0 0 * 1 A 6 0 0 * 1 A 5 0 0 * 1 A 4 0 0 * 1 A 3 0 0 * 1 A 2 0 0 * 1 A 1 0 1 * 1
Note: * Divide ratio (A) range = 0 to 127 Table. 6 Prescaler Data Setting SW = "H" Prescaler divide ratio IF-PLL RF-PLL 16/17 64/65 SW = "L" 32/33 128/129
Table. 7 Phase Comparator Phase Switching Data Setting FCIF,RF = H DoIF,RF fr > fp fr = fp fr < fp VCO polarity H Z L (1) FCIF,RF = L DoIF,RF L Z H (2)
(2) VCO Input Voltage VCO Output Frequency (1)
Note: * Z = High-impedance * Depending upon the VCO and LPF polarity, FC bit should be set.
Table. 8 LD/fout Output Select Data Setting LDS H L LD/fout output signal fout (frIF/RF, fpIF/RF) signals LD signal
10
MB15F03L
Serial Data Input Timing
1st. data 2nd. data
Control bit
Invalid data
Data
MSB
LSB
Clock t1 t7 LE t3 t6 t2 t5 t4
On rising edge of the clock, one bit of the data is transferred into the shift register.
Parameter
t1 t2 t3 t4
Min
20 20 30 20
Typ - - - -
Max - - - -
Unit
ns ns ns ns
Parameter
t5 t6 t7
Min
30 100 100
Typ - - -
Max - - -
Unit
ns ns ns
11
MB15F03L
s PHASE DETECTOR OUTPUT WAVEFORM
frIF/RF
fpIF/RF
tWU LD (FC bit = High) H DoIF/RF Z
tWL
L
(FC bit = Low) DoIF/RF Z
LD Output Logic Table
IF-PLL section
Locking state / Power saving state Locking state / Power saving state Unlocking state Unlocking state
RF-PLL section
Locking state / Power saving state Unlocking state Locking state / Power saving state Unlocking state
LD output
H L L L
Note: *Phase error detection range = -2 to +2 *Pulses on DoIF/RF signals are output to prevent dead zone. *LD output becomes low when phase error is tWU or more. *LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more. *tWU and tWL depend on OSCin input frequency as follows. tWU > 4/fosc: i.e. tWU > 312.5ns when foscin = 12.8 MHz tWL < 8/fosc: i.e. tWL < 625.0ns when foscin = 12.8 MHz
12
MB15F03L
s POWER SAVING MODE (INTERMITTENT MODE CONTROL CIRCUIT)
Setting a PSIF(RF) pin to Low, IF-PLL (RF-PLL) enters into power saving mode resultant current consumption can be limited to 10A (typ.). Setting PS pin to High, power saving mode is released so that the device works normally. In addition, the intermittent operation control circuit is included which helps smooth start up from stand by mode. In general, the power consumption can be saved by the intermittent operation that powering down or waking up the synthesizer. Such case, if the PLL is powered up uncontrolled, the resulting phase comparator output signal is unpredictable due to an undefined phase relation between reference frequency (fr) and comparison frequency (fp) and may in the worst case take longer time for lock up of the loop. To prevent this, the intermittent operation control circuit enforces a limited error signal output of the phase detector during power up. Thus keeping the loop locked. PS pin must be set "L" at Power-ON. Allow 1 s after frequency stabilization on power-up for exiting the power saving mode (PS: L to H) Serial data can be entered during the power saving mode. During the power saving mode, the corresponding section except for indispensable circuit for the power saving function stops working, then current consumption is reduced to 10A per one PLL section. At that time, the Do and LD become the same state as when a loop is locking. That is, the Do becomes high impedance. A VCO control voltage is naturally kept at the locking voltage which defined by a LPF's time constant. As a result of this, VCO's frequency is kept at the locking frequency.
PSIF L H L H
PSRF L L H H
IF-PLL counters OFF ON OFF ON
RF-PLL counters OFF OFF ON ON
OSC input buffer OFF ON ON ON
ON
Vcc Clock Data LE PS (1) (2) (3)
(1) PS = L (power saving mode) at Power-ON (2)Set serial data after power supply remains stable. (3)Release saving mode(PS : L H) after setting serial data.
13
MB15F03L
s TEST CIRCUIT (PRESCALER INPUT/PROGRAMMABLE REFERENCE DIVIDER INPUT SENSITIVITYTEST)
fout Oscilloscope VccIF 0.1F 1000pF S.G 50 1000pF GND 8 50 7 6 5 4 3 2 1
S.G
MB15F03L
9 S.G 1000pF 50
10
11
12
13
14
15
16
VccRF 1000pF Note.:SSOP-16 pin. 0.1F
Controller (divide ratio setting)
14
MB15F03L
s TYPICAL CHARACTERISITICS
1. fin Input Sensitivity
V fin RF vs. fin RF 10 5 0 Vfin RF (dBm) -5 -10 -15 -20 -25 -30 -35 -40 0 1000 2000 fin RF (MHz) V fin IF vs. fin IF 10 5 0 -5 Vfin IF (dBm) -10 -15 -20 -25 -30 -35 -40 0 100 200 300 400 500 fin IF (MHz) 600 700 800 900 1000 V CC = 2.7 V V CC = 3.0 V V CC = 3.6 V SPEC Ta = +25C 3000 4000 V CC = 2.7 V V CC = 3.0 V V CC = 3.6 V SPEC Ta = +25C
2. OSCin Input Characteristics
V fosc vs. fosc 10 5 0 -5 V fOSC (dBm) -10 -15 -20 -25 -30 -35 -40 -45 -50 0 10 20 30 40 50 60 70 80 90 100 fOSC (MHz) V CC = 2.7 V V CC = 3.0 V V CC = 3.6 V SPEC Ta = +25C
15
MB15F03L
3. DoRF Output Current
I DOH vs. V DOH
5.000
V CC = 3 V Ta = +25C
"H" level output voltage V DOH (V) .0000 .0000 "H" level output current I DOH (mA )
-25.00
I DOL vs. V DOL 5.000 V CC = 3 V Ta = +25C "L" level output voltage V DOL (V) .0000 .0000 "L" level output current I DOL (mA)
25.00
16
MB15F03L
4. DoIF Output Current
I DOH vs. V DOH
5.000
V CC = 3 V Ta = +25C
"H" level output voltage V DOH (V) .0000 .0000 "H" level output current I DOH (mA)
-25.00
I DOL vs. V DOL
5.000
V CC = 3 V Ta = +25C
"L" level output voltagee V DOL (V) .0000 .0000 "L" level output current I DOL (mA)
25.00
17
MB15F03L
5. Input Impedance.
fin RF Input Inpedance characteristic
1:
21 -144.73 500 MHz 10.471 -59.998 1 GHz 10.063 -24.667 1.5 GHz 11.614 -9.771 1.8 GHz
2:
3:
4
RF
4:
3
1
2
START 100.000 000 MHz STOP 2 000.000 000 MHz
fin IF Input Inpedance characteristic
1:
781.75 -918.94 50 MHz 57.344 -304.14 250 MHz 87.141 -377.39 200 MHz 26.633 -188.91 400 MHz
2:
3:
IF
4:
START 50.000 000 MHz
STOP 500.000 000 MHz
(Continued)
18
MB15F03L
(Continued)
OSC IN Input Impedance characteristic
1:
7.533 k -23.111 k 3 MHz 333 -6.2538 k 10 MHz 162.38 -2.9799 k 20 MHz 78.13 -1.5573 k 40 MHz
2:
3:
4
OSCIN
1 2 3
4:
START 1.000 000 MHz
STOP 50.000 000 MHz
19
MB15F03L
s APPLICATION EXAMPLE
Output VCO 3V from controller 1000 pF 0.1mF 1000 pF LPF
Clock 16
Data 15
LE 14
finRF 13
VccRF 12
XfinRF 11
PSRF 10
DoRF 9
MB15F03L
1
2
3 GNDIF
4 finIF
5 VccIF
6
7 PSIF
8 DoIF
GNDRF OSCIN
LD/fout
3V 1000 pF 1000 pF 0.1F TCXO Lock Det.
Output VCO LPF
Clock, Data, LE: Schmitt trigger circuit is provided (insert a pull-down or pull-up resistor to prevent oscillation when open-circuited in the input).
Note.:SSOP-16 pin
20
MB15F03L
s ORDERING INFORMATION
Part number MB15F03L PFV MB15F03L PV Package 16pin, Plastic SSOP (FPT-16P-M05) 16pin, Plastic BCC (LCC-16P-M03) Remarks
21
MB15F03L
s PACKAGE DIMENSION
16 pins, Plastic SSOP (FPT-16P-M05)
* 5.000.10(.197.004)
* : These dimensions do not include resin protrusion.
1.25 -0.10 +.008 .049 -.004
+0.20
0.10(.004)
INDEX
*4.400.10
(.173.004)
6.400.20 (.252.008)
5.40(.213) NOM
0.650.12 (.0256.0047)
0.22 -0.05 +.004 .009 -.002
+0.10
"A"
0.15 -0.02 +.002 .006 -.001
+0.05
Details of "A" part 0.100.10(.004.004) (STAND OFF)
4.55(.179)REF
0
10
0.500.20 (.020.008)
Dimensions in mm (inches)
C
1994 FUJITSU LIMITED F16013S-2C-4
(Continued)
22
MB15F03L
(Continued)
16 pins, Plastic BCC (LCC-16P-M03)
4.550.10 (.179.004) 0.80(.032)MAX
9
* : These dimensions do not include resin protrusion.
3.40(.134)TYP
9
14
(Mounting height)
0.65(.026)TYP
14
0.400.10 (.016.004) 4.200.10 (.165.004) 45 3.25(.128) TYP "A" "B" 1.55(.061)TYP
0.80(.032) TYP
1
E-MARK
6
0.40(.016) 0.0850.040 (.003.002) (STAND OFF)
6
0.3250.10 (.013.004)
1.725(.068) TYP
1
Details of "A" part 0.750.10 (.030.004) 0.05(.002)
Details of "B" part 0.600.10 (.024.004)
0.400.10 (.016.004)
0.600.10 (.024.004)
C
1996 FUJITSU LIMITED C16014S-1C-1
Dimensions in mm (inches)
23
MB15F03L
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3753 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: 1-800-866-8608 Customer Response Center Fax:1-408 -922-9179 Mon-Fri: 7am-5pm (PST) Internet URL: http://www.fujitsumicro.com Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281 0770 Fax: (65) 281 0220
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F9705 (c) FUJITSU LIMITED
Printed in Japan
TC-DS-20516-10/97
24

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